1) Field of the Invention
The present invention relates to a multi-port memory circuit, for example, such as a FIFO (First In First Out) memory.
2) Description of the Related Art
A FIFO memory is used for various applications as a data buffer between devices that are different in operation speed. The FIFO memory is a two-port memory in which a read clock is not synchronized to a write clock. The conventional FIFO memory is formed of a dynamic random access memory(DRAM) including three transistors and one capacitor per memory cell, or a static random access memory (SRAM) including eight transistors per memory cell.
Hereafter, outline of the conventional FIFO memory will be explained with reference to FIGS. 9 to 11. FIG. 9 is a block diagram that shows a typical configuration of the FIFO memory. FIG. 10 is a block diagram that shows a configuration of memory cells and peripheral circuits that correspond to one address of a DRAM FIFO memory including three transistors and one capacitor per memory cell. FIG. 11 is a block diagram that shows a configuration of memory cells and peripheral circuits that correspond to one address of a SRAM FIFO memory including eight transistors per memory cell.
In the FIFO memory, a write word decoder 92 is provided on a first end side in a row direction of a memory cell array 91 to write data, and a read word decoder 94 is provided on a second end side in the row direction to read data, as shown in FIG. 9. A write bit decoder 93 is provided on a first end side in a column direction of the memory cell array 91 to write data, and a read bit decoder 95 is provided on a second end side in the column direction to read data. Owing to this configuration, it is possible to cope with a write clock and a read clock that are asynchronously input. Memory cells 96 that correspond to one address typically include approximately 8 bits, i.e., 8 memory cells. Each of FIGS. 10 and 11 shows memory cells of 8 bits and their peripheral circuits.
In memory cells 101 of an address n shown in FIG. 10, a memory cell of zeroth bit 101-0 to a memory cell of seventh bit 101-7 are arranged on one lateral line. The memory cells 101 include a two-input NOR circuit 102. As peripheral circuits, write drivers 104-0 to 104-7 and sense amplifiers 105-0 to 105-7 are provided every eight memory cells. PMOS transistors 108-0 to 108-7 and 109-0 to 109-7 that form precharge circuits are provided so as to correspond to the write drivers 104-0 to 104-7 and the sense amplifiers 105-0 to 105-7. Write bit lines WBL<0> to WBL<7> are connected to input terminals of the write drivers 104-0 to 104-7. Read bit lines RBL<0> to RBL<7> are connected to output terminals of the sense amplifiers 105-0 to 105-7.
Gate electrodes of the PMOS transistors 108-0 to 108-7 and 109-0 to 109-7 are connected to a precharge enforcement line. Source electrodes of the PMOS transistors 108-0 to 108-7 and 109-0 to 109-7 are connected to a power supply 107. Drain electrodes of the PMOS transistors 108-0 to 108-7 are connected to output terminals of the write drivers 104-0 to 104-7, respectively. Drain electrodes of the PMOS transistors 109-0 to 109-7 are connected to input terminals of the sense amplifiers 105-0 to 105-7, respectively.
In the memory cells 101 of the address n, a write word select line WWS and a read word select line RWS are disposed in the row direction. A write bit select line WBS is disposed in the column direction. A first input terminal of the NOR circuit 102 is connected to the write word select line WWS. A second input terminal of the NOR circuit 102 is connected to the write bit select line WBS.
Eight memory cells 101-0 to 101-7 have the same configuration. Each of the memory cells 101-0 to 101-7 has three NMOS transistors 111, 112 and 113, and one capacitor 114. In other words, each of the memory cells 101-0 to 101-7 is a DRAM memory cell having three transistors and one capacitor.
The NMOS transistor 111 is connected at its gate electrode serving as a select terminal to an output line of the NOR circuit 102, connected at its source electrode to a storage node of the capacitor 114, and connected at its drain electrode to associated one of connection lines (hereafter referred to as write bit lines WBL<0> to WBL<7>) respectively between output terminals of the write drivers 104-0 to 104-7 and the drain electrodes of the NMOS transistors 108-0 to 108-7.
The NMOS transistor 112 is connected at its gate electrode to the storage node of the capacitor 114, connected at its source electrode to ground, and connected at its drain electrode to the NMOS transistor 113 at its source electrode. The NMOS transistor 113 is connected at its gate electrode serving as a select terminal to the read word select line RWS, and connected at its drain electrode to associated one of connection lines (hereafter referred to as read bit lines RBL<0> to RBL<7>) respectively between input terminals of the sense amplifiers 105-0 to 105-7 and the drain electrodes of the PMOS transistors 109-0 to 109-7.
In the configuration, the write bit lines (WBL<0> to WBL<7>) and the read bit lines (RBL<0> to RBL<7>) are precharged to assume a high level (hereafter referred to as “H” level) respectively before write operation and read operation are started.
At the time of write operation, an address on an intersection of a write word select line WWS and a write bit select line WBS is selected. In the example of FIG. 10, the address n (the memory cells 101) is selected. Only the NOR circuit 102 of the selected address n outputs the “H” level. As a result, the NMOS transistors 111 turn on. Accordingly, the memory cell 101-0 of the zeroth bit to the memory cell 101-7 of the seventh bit become active en bloc, and data write operation is conducted.
At the time of read operation, the NMOS transistors 113 are turned ON by the read word select line RWS. Accordingly, all addresses in the column direction are selected en bloc. However, the sense amplifiers 105-0 to 105-7 that correspond to the selected address n are activated. Data of eight bits stored in the memory cell 101-0 of the zeroth bit to the memory cell 101-7 of the seventh bit in the address n are read to outside. The read operation of the DRAM memory cells is nondestructive read. Therefore, the data can be read out many times as long as it is in the data holding time.
In memory cells 121 of an address n shown in FIG. 11, a memory cell of zeroth bit 121-0 to a memory cell of seventh bit 121-7 are arranged on one lateral line. As peripheral circuits, write drivers 122-0 to 122-7 and sense amplifiers 123-0 to 123-7 are provided every eight memory cells. PMOS transistors 128-0 to 128-7 and 129-0 to 129-7 that form precharge circuits are provided so as to correspond to the write drivers 122-0 to 122-7 and the sense amplifiers 123-0 to 123-7.
The write drivers 122-0 to 122-7 respectively include write drivers 131-0 to 131-7 connected at their input terminals to write bit lines WBL<0> to WBL<7>, and write drivers 132-0 to 132-7 connected at their input terminals to write bit lines WBLB<0> to WBLB<7>. Output terminals of the write drivers 132-0 to 132-7 are connected to input terminals of the sense amplifiers 123-0 to 123-7, respectively. Read bit lines RBL<0> to RBL<7> are connected to output terminals of the sense amplifiers 123-0 to 123-7, respectively.
Gate electrodes of the PMOS transistors 128-0 to 128-7 and 129-0 to 129-7 are connected to a precharge enforcement line. Source electrodes of the PMOS transistors 128-0 to 128-7 and 129-0 to 129-7 are connected to a power supply 127. Drain electrodes of the PMOS transistors 128-0 to 128-7 are connected to output terminals of the write drivers 131-0 to 131-7, respectively. Drain electrodes of the PMOS transistors 129-0 to 129-7 are connected to the output terminals of the write drivers 132-0 to 132-7 and the input terminals of the sense amplifiers 123-0 to 123-7, respectively.
In the memory cells 101 of the address n, a write word select line WWS and a read word select line RWS are disposed in the row direction. Eight memory cells 121-0 to 121-7 have the same configuration. Each of the memory cells 121-0 to 121-7 includes a storage element 132 represented by anti-parallel connection of inverters, and NMOS transistors 131, 133, 134 and 135. Each of the inverters included in the storage element 132 has two NMOS transistors. Therefore, each of the memory cells 121-0 to 121-7 is an SRAM memory cell that has eight NMOS transistors in all.
The NMOS transistor 131 is connected at its gate electrode serving as a select terminal to the write word select line WWS, connected at its source electrode to a first node of the storage element 132, and connected at its drain electrode to associated one of connection lines respectively between the output terminals of the write drivers 131-0 to 131-7 and the drain electrodes of the NMOS transistors 128-0 to 128-7.
The NMOS transistor 133 is connected at its gate electrode serving as a select terminal to the write word select line WWS, connected at its source electrode to a second node of the storage element 132, and connected at its drain electrode to the NMOS transistor 135 at its drain electrode and to associated one of connection lines respectively among the output terminals of the write drivers 132-0 to 132-7, the input terminals of the sense amplifiers 123-0 to 123-7, and the drain electrodes of the PMOS transistors 129-0 to 129-7. In other words, the write bit lines WBLB<0> to WBLB<7> respectively connected to the input terminals of the write drivers 132-0 to 132-7 respectively join the read bit lines RBL<0> to RBL<7>, and are connected to the memory cells 121-0 to 121-7, respectively.
The NMOS transistor 134 is connected at its gate electrode to the second node of the storage element 132 together with the source electrode of the NMOS transistor 133, and connected at its source electrode to ground. The NMOS transistor 135 is connected at its gate electrode serving as a select terminal to the read word select line RWS, and connected at its source electrode to the NMOS transistor 134 at its drain electrode.
In the configuration, the write bit lines and the read bit lines are precharged to assume the “H” level respectively before write operation and read operation are started. At the time of write operation, the NMOS transistors 131 and 133 are turned ON by the write word select line WWS. All addresses in the column direction are selected en bloc. However, the write drivers 122-0 to 122-7 selected by eight write bit lines that pass through the address n to be written are activated. Write operation to the address n is conducted. In the SRAM, only data of a low level (hereafter referred to as “L” level) can be written because of its structure. Therefore, the write drivers 131-0 to 131-7 are selected by the write bit lines WBL<0> to WBL<7> and the write drivers 132-0 to 132-7 are selected by the write bit lines WBLB<0> to WBLB<7>, and thereby write operation is conducted.
At the time of read operation, the NMOS transistors 135 are turned ON by the read word select line RWS. Accordingly, all addresses in the column direction are selected en bloc. However, the sense amplifiers 123-0 to 123-7 that correspond to the selected address n are activated. Data of eight bits stored in the memory cell 101-0 of the zeroth bit to the memory cell 101-7 of the seventh bit in the address n are read to outside. The read operation of the SRAM memory cells is nondestructive read. Therefore, the data can be read out many times. There is no problem of data holding.
In the FIFO memory using the SRAM memory cells, there is no restriction on data holding time. Since the number of transistors is large, however, the area of memory cells becomes larger than that of DRAM memory cells. Thus, it is difficult to reduce the chip size.
On the other hand, the FIFO memory using the DRAM memory cells can be reduced in size than the FIFO memory using the SRAM memory cells. However, a NOR circuit serving as the write select circuit is needed per address. When the number of bits per address is small, therefore, the proportion of the NOR circuit in the area of the memory cell becomes large. In addition, when there is no refresh circuit as shown in FIG. 10, there is a problem of a full-time restriction of the data holding time.